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Espressif Systems /ESP32-C3 /UART0 /CLK_CONF

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Interpret as CLK_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SCLK_DIV_B0SCLK_DIV_A0SCLK_DIV_NUM0SCLK_SEL 0 (SCLK_EN)SCLK_EN 0 (RST_CORE)RST_CORE 0 (TX_SCLK_EN)TX_SCLK_EN 0 (RX_SCLK_EN)RX_SCLK_EN 0 (TX_RST_CORE)TX_RST_CORE 0 (RX_RST_CORE)RX_RST_CORE

Description

UART core clock configuration

Fields

SCLK_DIV_B

The denominator of the frequency divider factor.
SCLK_DIV_A

The numerator of the frequency divider factor.
SCLK_DIV_NUM

The integral part of the frequency divider factor.
SCLK_SEL

UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
SCLK_EN

Set this bit to enable UART Tx/Rx clock.
RST_CORE

Write 1 then write 0 to this bit, reset UART Tx/Rx.
TX_SCLK_EN

Set this bit to enable UART Tx clock.
RX_SCLK_EN

Set this bit to enable UART Rx clock.
TX_RST_CORE

Write 1 then write 0 to this bit, reset UART Tx.
RX_RST_CORE

Write 1 then write 0 to this bit, reset UART Rx.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd